[git commit] import specs from old svn repo
Mike Frysinger
vapier at gentoo.org
Sat May 5 07:46:59 UTC 2012
commit: http://git.uclibc.org/uClibc-website/commit/?id=7a0b311cfbbb2688a0b65909628c1e467407d3d2
branch: http://git.uclibc.org/uClibc-website/commit/?id=refs/heads/master
Signed-off-by: Mike Frysinger <vapier at gentoo.org>
---
docs/SysV-ABI.pdf | Bin 0 -> 845798 bytes
docs/SysV-Interface-vol1a.pdf | Bin 0 -> 2262323 bytes
docs/SysV-Interface-vol1b.pdf | Bin 0 -> 368774 bytes
docs/SysV-Interface-vol2.pdf | Bin 0 -> 1383378 bytes
docs/elf-64-gen.pdf | Bin 0 -> 172444 bytes
docs/elf.pdf | Bin 0 -> 345215 bytes
docs/psABI-arm.pdf | Bin 0 -> 281269 bytes
docs/psABI-i386.pdf | Bin 0 -> 1068001 bytes
docs/psABI-ia64.pdf | Bin 0 -> 723623 bytes
docs/psABI-m8-16.pdf | Bin 0 -> 50614 bytes
docs/psABI-mips.pdf | Bin 0 -> 490809 bytes
docs/psABI-parisc.pdf | Bin 0 -> 175702 bytes
docs/psABI-ppc.pdf | Bin 0 -> 267313 bytes
docs/psABI-ppc64.pdf | Bin 0 -> 345543 bytes
docs/psABI-s390.pdf | Bin 0 -> 397520 bytes
docs/psABI-s390x.pdf | Bin 0 -> 397970 bytes
docs/psABI-sh.txt | 411 +++++++++++++++++++++++++++++++
docs/psABI-sparc.pdf | Bin 0 -> 388643 bytes
docs/psABI-x86_64.pdf | Bin 0 -> 342798 bytes
docs/tls-ppc.txt | 299 ++++++++++++++++++++++
docs/tls-ppc64.txt | 547 +++++++++++++++++++++++++++++++++++++++++
docs/tls.pdf | Bin 0 -> 630410 bytes
header.html | 1 +
specs.html | 79 ++++++
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@@ -0,0 +1,411 @@
+We wrote this note as a diff to the i386 version of the supplement.
+
+----
+System V ABI SH-3/SH-4 Architecture Processor Supplement
+
+
+1. Introduction
+
+2. Software Installation
+
+3. Low-level System Information
+
+ Operating System Interface
+ Virtual Address Space
+ Page Size
+ Virtual Address Assignment
+
+----
+Figure 3-xx: Virtual Address Configuration
+
+ Reserved End of memory
+ 0x7bffffff Stack and
+ dynamic segments
+
+
+ 0 Lodable segments Beginning of memory
+----
+
+ Process Stack and Registers
+
+ The registers listed below have the specified contents at
+ process entry:
+
+ r0 A non-zero value specifies a function pointer the application
+ should register with atexit(BA_OS). If r0 contains zero, no
+ action is required.
+ r15 The stack pointer holds the address of the bottm of the stack
+ which must be doubleword(8-byte) aligend.
+ pr The return address register is set to zero.
+
+ Code Model Overview
+
+ We denote the register pointing the global offset table as GP.
+ GP is NOT specified in this supplement and may be gbr or one of
+ the general registers. We assume that R12 is GP in this supplement
+ for examples.
+
+ name at GOT
+ This expression denotes a GP-relative reference to the global
+ offset table entry for the symbol name. The GP register contains
+ the absolute address of the global offset table.
+ name at GOTOFF
+ This expression denotes a GP-relative reference to the symbol
+ name.
+ name at PLT
+ This expression denotes a PC-relative reference to the procedure
+ linkage table entry for the symbol name.
+ _GLOBAL_OFFSET_TABLE_
+ The symbol _GLOBAL_OFFSET_TABLE_ is used to access the global
+ offset table. When an instruction uses the symbol, it sees the
+ offset between the current instruction and the global offset table
+ as the symbol value.
+
+ Position-Independent Function Prologue and Epilogue
+
+ We give examples position-independent code using GP register as
+ the global pointer register, though the global pointer register
+ is depending on the specific compiler.
+
+----
+Figure 3-xx: Podition-Independent Function Prologue
+
+ mov.l 1f,r1
+ mova 1f,r12
+ bra 2f
+ add r1,r12 ! GOT-pc+pc --> GOT
+ .align 2
+1: .long _GLOBAL_OFFSET_TABLE_
+2: ...
+----
+ This code above could be optimized. The .long _GLOBAL_OFFSET_TABLE_
+ pseudo instruction may be moved to the afterword to save the branch
+ on function entry.
+
+----
+Figure 3-xx: Podition-Independent Function Epilogue
+ ...
+----
+
+ Data Objects
+
+----
+Figure 3-xx: Podition-independent Data Access
+
+ C Assembly
+
+ extern int src; .globl src, dst, ptr
+ extern int dst;
+ extern int *ptr;
+ ptr = &dst; mov.l 1f,r0
+ mov.l @(r0,r12),r2
+ mov.l 2f,r0
+ mov.l @(r0,r12),r3
+ mov.l r3, at r2
+
+
+ ... ...
+
+ *ptr = src; mov.l 1f,r0
+ mov.l @(r0,r12),r2
+ mov.l 3f,r0
+ mov.l @(r0,r12),r3
+ mov.l @r2,r4
+ mov.l @r3,r5
+ mov.l r5, at r4
+ ...
+
+ 1: .long ptr at GOT
+ 2: .long dst at GOT
+ 3: .long src at GOT
+
+----
+----
+Figure 3-xx: Podition-independent Static Data Access
+
+ C Assembly
+
+ static int src;
+ static int dst;
+ static int *ptr;
+ ptr = &dst; mov.l 1f,r0
+ mov.l 2f,r2
+ add r12,r2
+ mov.l r2,@(r0,r12)
+ ... ...
+
+ *ptr = src; mov.l 1f,r0
+ mov.l @(r0,r12),r2
+ mov.l 3f,r0
+ mov.l @(r0,r12),r3
+ mov.l r3, at r2
+ ...
+
+ 1: .long ptr at GOTOFF
+ 2: .long dst at GOTOFF
+ 3: .long src at GOTOFF
+
+----
+ Those code above could be optimized.
+
+
+ Function Calls
+
+----
+Figure 3-xx: Podition-independent Direct Function Call
+
+ C Assembly
+
+ extern void foo (); .globl foo
+ foo (); mov.l 1f,r1
+ mova 1f,r0
+ add r0,r1
+ jsr @r1
+ ...
+
+ 1: .long foo at PLT
+
+ An implementation may also do direct PIC calls using bsrf
+
+ C Assembly
+
+ extern void foo (); .globl foo
+ foo (); mov.l 1f,r1
+ bsrf r1
+ nop
+ 2:
+ ...
+ 1: .long .-2b+foo at PLT
+----
+----
+Figure 3-xx: Podition-independent Indirect Function Call
+
+ C Assembly
+
+ extern void foo (); .globl foo, ptr
+ extern void (*ptr) ();
+
+ ptr = foo; mov.l 1f,r0
+ mov.l @(r0,r12),r2
+ mov.l 2f,r0
+ mov.l @(r0,r12),r3
+ mov.l r2, at r3
+ ... ...
+
+ (*ptr) (); mov.l 2f,r0
+ mov.l @(r0,r12),r2
+ mov.l @r2,r0
+ jmp @r0
+ ...
+
+ 1: .long foo at GOT
+ 2: .long ptr at GOT
+----
+ Those code above could be optimized.
+
+
+ Branching
+
+4. Object Files
+
+ ELF Header
+ Sections
+ Special Sections
+ .got
+ .plt
+ Symbol Table
+ Relocation
+ Relocation Types
+
+----
+
+A This means the addend used to compute the value of the relocatable field.
+
+B This means the base address at which shared object has been loaded into
+ memory during execution.
+
+G This means the offset into the global offset table at which the address
+ of the relocation entry's symbol will resides during execution.
+
+GOT This means the address of the global offset table.
+
+L This means the place (section offset or address) of the procedure linkage
+ table entry for a symbol.
+
+P This means the place (section offset or address) of the strage unit being
+ relocated (computed using r_offset).
+
+S This means the value of the symbol whose index resides in the relocation
+ entry.
+
+Figure 4-xx: Relocation Types
+
+ Name Value Field Calculation
+(base)R_SH_NONE 0 none none
+ R_SH_DIR32 1
+ R_SH_REL32 2
+ R_SH_DIR8WPN 3
+ R_SH_IND12W 4
+ R_SH_DIR8WPL 5
+ R_SH_DIR8WPZ 6
+ R_SH_DIR8BP 7
+ R_SH_DIR8W 8
+ R_SH_DIR8L 9
+
+
+(new) R_SH_GOT32 0xa0 word32 G + A - P
+ R_SH_PLT32 0xa1 word32 L + A - P
+ R_SH_COPY 0xa2 none none
+ R_SH_GLOB_DAT 0xa3 word32 S
+ R_SH_JMP_SLOT 0xa4 word32 S
+ R_SH_RELATIVE 0xa5 word32 B + A
+ R_SH_GOTOFF 0xa6 word32 S + A - GOT
+ R_SH_GOTPC 0xa7 word32 GOT - A - P
+
+ Some relocation types have semantics beyond simple calculation.
+
+R_SH_GOT32
+ This relocation type computes the distance from the base of the global
+ offset table to the symbol's global offset table entry. It additionally
+ instructs the link editor to build a global offset table.
+
+R_SH_PLT32
+ This relocation type computes the address of the symbol's procedure
+ linkage table entry and additionally instructs the linkage editor to
+ build a global offset table.
+
+R_SH_COPY
+ The link editor creates this relocation type for dynamic linking.
+ Its offset member refers to a location in a writtable segment. The
+ symbol table index specifies a symbol that should exist both in the
+ current object file and in a shared object. During execution, the
+ dynamic linker copies data associaated with the shared object's symbol
+ to the location specified by the offset.
+
+R_SH_GLOB_DAT
+ This relocation type used to set a global offset table entry to the
+ address of the specified symbol. The special relocation type allows
+ one to determine the correspondence between symbols and global offset
+ table entries.
+
+R_SH_JMP_SLOT
+ The link editor creates this relocation type for dynamic linking.
+ Its offset member gives the location of a procedure linkage table entry.
+ The dynamic linker modifies the procedure linkage table to transfer
+ control to the designated symbol's address.
+
+R_SH_RELATIVE
+ The link editor creates this relocation type for dynamic linking.
+ Its offset member gives the location within a shred object that contains
+ a value representing a relative offset. The dynamic linker computes
+ the corresponding virtual address by adding the virtual address at which
+ the shared object was loaded to the relative address. Relocation entries
+ for this type must specify 0 for the symbol index.
+
+R_SH_GOTOFF
+ This relocation type computes the difference between a symbol's value
+ and the address of the global offset table. It additionally instructs
+ the link editor to build a global offset table.
+
+R_SH_GOTPC
+ This relocation type resembles R_SH_REL32, except it uses the address
+ of the global offset table in its calculation. The symbol referenced
+ in this relocation normally is _GLOBAL_OFFSET_TABLE_, which additionally
+ instructs the link editor to build a global offset table.
+
+----
+
+5. Program Loading and Dynamic Linking
+
+ Program Loading
+ Dynamic Linking
+ Dynamic Section
+ Global Offset Table
+ Function Linkage Table
+
+----
+Figure 5-xx: PLT implementations
+
+Absolute 32-bit version:
+--------------------------
+.PLT0: mov.l 2f,r2
+ mov.l 1f,r0
+ mov.l @r0,r0
+ mov.l @r2,r2
+ jmp @r0
+ mov #0,r0
+ nop
+ nop
+ nop
+ nop
+1: .long .got + 8
+2: .long .got + 4
+
+.PLTn: mov.l 1f,r0
+ mov.l 3f,r2
+ jmp @r0
+ mov r2,r0
+3: .long .PLT0
+0: mov.l 2f,r1
+ jmp @r0
+ nop
+ nop
+1: .long nameN-in-GOT
+2: .long relocation-table-address
+--------------------------
+
+Position-Independent 32-bit version:
+--------------------------
+.PLTn: mov.l 1f,r0
+ mov.l @(r0,r12),r0
+ jmp @r0
+ nop
+0: mov.l @(8,r12),r0 ! dynamic linker address
+ mov.l @(4,r12),r2 ! argument to the linker (id of GOT)
+ mov.l 2f,r1 ! argument to the linker (reloc offset)
+ jmp @r0
+ mov #0,r0 ! here is the MAGIC
+ nop ! pad
+1: .long nameN at GOT
+2: .long relocation-table-address
+--------------------------
+
+Position-Independent 16-bit version:
+--------------------------
+.PLTn: mov.w 1f,r0
+9: mov.l @(r0,r12),r0 ! NOTE! this statement has double meanings
+ jmp @r0
+0: mov #8,r0 ! NOTE! this statement has double meanings
+ mov.l 2f,r1 ! argument to the linker (reloc number)
+ bra 9b
+ mov.l @(4,r12),r2 ! argument to the linker (id of GOT)
+1: .word nameN at GOT
+2: .word entry-number-of-relocation-table
+--------------------------
+ Those code above could be optimized.
+
+----
+
+ Dynamic linker can distinguish which version of PLT as follows:
+
+ In case of 32-bit version PLT:
+ r0 = 0
+ r1 = relocation-table-address
+ r2 = GOT id
+ In case of 16-bit version PLT:
+ r0 = 8
+ r1 = entry-number-of-relocation-table
+ r2 = GOT id
+
+ Here, the type of PLT is encoded into R0. Dynamic linker may or
+ may not use the value of R0.
+
+
+ Program Interpreter
+
+
+6. Libraries
+
+7. Developement Environment
+
+8. Execution Environment
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diff --git a/docs/tls-ppc.txt b/docs/tls-ppc.txt
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+++ b/docs/tls-ppc.txt
@@ -0,0 +1,299 @@
+PowerPC Specific Thread Local Storage ABI
+For insertion in http://people.redhat.com/drepper/tls.pdf
+
+
+3.4.x PowerPC32 Specific
+-------------------------
+
+The PowerPC32 TLS ABI is similar to the PowerPC64 model. The thread-local
+storage data structures follow variant I. The TCB is 8 bytes, with the
+first 4 bytes containing the pointer to the dynamic thread vector.
+tlsoffset calculations and definition of __tls_get_addr are identical to
+PowerPC64. r2 is the thread pointer, and points 0x7000 past the end of the
+thread control block. Dynamic thread vector pointers point 0x8000 past the
+start of each TLS block. (*) This allows the first 64K of each block to
+be addressed from a dtv pointer using fewer machine instructions. The tp
+offset allows for efficient addressing of the TCB and up to 4K-8 of other
+thread library information.
+
+(*) For implementation reasons the actual value stored in dtv may point to
+the start of a block, however values returned by accessor functions will be
+offset by 0x8000.
+
+
+4.1.x PowerPC32 General Dynamic TLS Model
+------------------------------------------
+
+The PowerPC32 general dynamic access model is similar to that for PowerPC64.
+The __tls_get_addr function is called with one parameter which is a pointer
+to an object of type tls_index. In the following code it is assumed that
+register r31 points to the GOT. Different registers may well be used.
+
+Code sequence Reloc Sym
+ addi 3,31,x at got@tlsgd R_PPC_GOT_TLSGD16 x
+ bl __tls_get_addr R_PPC_REL24 __tls_get_addr
+
+GOT[n] R_PPC_DTPMOD32 x
+GOT[n+1] R_PPC_DTPREL32 x
+
+The relocation specifier @got at tlsgd causes the linker to create an object
+of type tls_index in the GOT. The address of this object is loaded into
+the first argument register with the addi instruction, then a standard
+function call is made.
+
+
+4.2.x PowerPC32 Local Dynamic TLS Model
+----------------------------------------
+
+This is similar to other architectures. Two different sequences may be
+used, depending on the size of the offset to the variable.
+
+Code sequence Reloc Sym
+ addi 3,31,x1 at got@tlsld R_PPC_GOT_TLSLD16 x1
+ bl __tls_get_addr R_PPC_REL24 __tls_get_addr
+..
+ addi 9,3,x1 at dtprel R_PPC_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC_DTPREL16_HA x2
+ addi 9,9,x2 at dtprel@l R_PPC_DTPREL16_LO x2
+
+GOT[n] R_PPC_DTPMOD32 x1
+GOT[n+1] 0
+
+ at got@tlsld in the first instruction causes the linker to generate a
+tls_index object in the GOT with a fixed 0 offset. The code shown assumes
+that x1 is in the first 64k of the thread storage block, while x2 isn't.
+If we wanted to load the values of x1 and x2 instead of the address, then
+we could access int variables with
+
+..
+ lwz 0,x1 at dtprel(3) R_PPC_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC_DTPREL16_HA x2
+ lwz 0,x2 at dtprel@l(9) R_PPC_DTPREL16_LO x2
+
+
+4.3.x PowerPC32 Initial Exec TLS Model
+---------------------------------------
+
+Code sequence Reloc Sym
+ lwz 9,x at got@tprel(31) R_PPC_GOT_TPREL16 x
+ add 9,9,x at tls R_PPC_TLS x
+
+GOT[n] R_PPC_TPREL32 x
+
+ at got@tprel in the first instruction causes the linker to generate a GOT
+entry with a relocation that the dynamic linker will replace with the
+offset for x relative to the thread pointer. x at tls tells the assembler to
+use an r2 form of the instruction (ie. add 9,9,2 in this case), and tag the
+instruction with a reloc that indicates it belongs to a TLS sequence. This
+may be later used by the linker when optimizing TLS code.
+
+To read the contents of the variable instead of calculating its address,
+the "add 9,9,x at tls" instruction might be replaced with "lwzx 0,9,x at tls".
+
+
+4.4.x PowerPC32 Local Exec TLS Model
+-------------------------------------
+
+Two different sequences may be used, depending on the size of the offset to
+the variable. The first one handles offsets within 60K of the end of the
+TLS block (remember that r2 points 28K past the end of the TCB, which is
+immediately prior to the first TLS block).
+
+Code sequence Reloc Sym
+ addi 9,2,x1 at tprel R_PPC_TPREL16 x1
+..
+ addis 9,2,x2 at tprel@ha R_PPC_TPREL16_HA x2
+ addi 9,9,x2 at tprel@l R_PPC_TPREL16_LO x2
+
+
+5.x PowerPC32 Linker Optimizations
+-----------------------------------
+
+The linker transformations for PowerPC32 are quite straightforward, since
+all the relevant code sequences are two instructions long.
+
+5.x.1 General Dynamic To Initial Exec
+--------------------------------------
+
+Code sequence Reloc Sym
+ addi 3,31,x at got@tlsgd R_PPC_GOT_TLSGD16 x
+ bl __tls_get_addr R_PPC_REL24 __tls_get_addr
+
+GOT[n] R_PPC_DTPMOD32 x
+GOT[n+1] R_PPC_DTPREL32 x
+
+is replaced by
+
+ lwz 3,x at got@tprel(31) R_PPC_GOT_TPREL16 x
+ add 3,3,2
+
+GOT[n] R_PPC_TPREL32 x
+
+The linker relies on this sequence being emitted without intervening
+instructions. A register other than r31 may be used as the GOT pointer.
+
+5.x.2 General Dynamic To Local Exec
+------------------------------------
+
+Code sequence Reloc Sym
+ addi 3,31,x at got@tlsgd R_PPC_GOT_TLSGD16 x
+ bl __tls_get_addr R_PPC_REL24 __tls_get_addr
+
+GOT[n] R_PPC_DTPMOD32 x
+GOT[n+1] R_PPC_DTPREL32 x
+
+is replaced by
+
+ addis 3,2,x at tprel@ha R_PPC_TPREL16_HA x
+ addi 3,3,x at tprel@l R_PPC_TPREL16_LO x
+
+The linker relies on this sequence being emitted without intervening
+instructions. A register other than r31 may be used as the GOT pointer.
+
+5.x.3 Local Dynamic to Local Exec
+----------------------------------
+
+In this case, the function call is replaced with an equivalent code
+sequence. As shown, following dtprel sequences are left unchanged.
+
+Code sequence Reloc Sym
+ addi 3,31,x1 at got@tlsld R_PPC_GOT_TLSLD16 x1
+ bl __tls_get_addr R_PPC_REL24 __tls_get_addr
+..
+ addi 9,3,x1 at dtprel R_PPC_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC_DTPREL16_HA x2
+ addi 9,9,x2 at dtprel@l R_PPC_DTPREL16_LO x2
+
+GOT[n] R_PPC_DTPMOD32 x1
+GOT[n+1]
+
+is replaced by
+
+ addis 3,2,L at tprel@ha R_PPC_TPREL16_HA linker generated local sym
+ addi 3,3,L at tprel@l R_PPC_TPREL16_LO linker generated local sym
+..
+ addi 9,3,x1 at dtprel R_PPC_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC_DTPREL16_HA x2
+ addi 9,9,x2 at dtprel@l R_PPC_DTPREL16_LO x2
+
+The "linker generated local sym" points to the start of the thread storage
+block plus 0x7000. In practice, a section symbol with a suitable offset
+will be used. The linker relies on code for the tls_get_addr call being
+emitted without intervening instructions. A register other than r31 may
+be used as the GOT pointer.
+
+5.x.4 Initial Exec To Local Exec
+---------------------------------
+
+Code sequence Reloc Sym
+ lwz 9,x at got@tprel(31) R_PPC_GOT_TPREL16 x
+ add 9,9,x at tls R_PPC64_TLS x
+
+GOT[n] R_PPC_TPREL32 x
+
+is replaced by
+
+ addis 9,2,x at tprel@ha R_PPC_TPREL16_HA x
+ addi 9,9,x at tprel@l R_PPC_TPREL16_LO x
+
+Other sizes and types of thread-local variables may use any of the X-FORM
+indexed loads or stores. The "lwz" and "add" instruction in this case may
+have intervening code inserted by the compiler.
+
+An example showing access to the contents of a variable:
+
+Code sequence Reloc Sym
+ lwz 9,x at got@tprel(31) R_PPC_GOT_TPREL16 x
+ lbzx 10,9,x at tls R_PPC_TLS x
+ addi 10,10,1
+ stbx 10,9,x at tls R_PPC_TLS x
+
+GOT[n] R_PPC_TPREL32 x
+
+is replaced by
+
+ addis 9,2,x at tprel@ha R_PPC_TPREL16_HA x
+ lbz 10,x at tprel@l(9) R_PPC_TPREL16_LO x
+ addi 10,10,1
+ stb 10,x at tprel@l(9) R_PPC_TPREL16_LO x
+
+
+6.x New PowerPC32 ELF Definitions
+----------------------------------
+
+Reloc Name Value Field Expression
+R_PPC_TLS 67 none (sym+add)@tls
+R_PPC_DTPMOD32 68 word32 (sym+add)@dtpmod
+R_PPC_TPREL16 69 half16* (sym+add)@tprel
+R_PPC_TPREL16_LO 60 half16 (sym+add)@tprel at l
+R_PPC_TPREL16_HI 71 half16 (sym+add)@tprel at h
+R_PPC_TPREL16_HA 72 half16 (sym+add)@tprel at ha
+R_PPC_TPREL32 73 word32 (sym+add)@tprel
+R_PPC_DTPREL16 74 half16* (sym+add)@dtprel
+R_PPC_DTPREL16_LO 75 half16 (sym+add)@dtprel at l
+R_PPC_DTPREL16_HI 76 half16 (sym+add)@dtprel at h
+R_PPC_DTPREL16_HA 77 half16 (sym+add)@dtprel at ha
+R_PPC_DTPREL32 78 word32 (sym+add)@dtprel
+R_PPC_GOT_TLSGD16 79 half16* (sym+add)@got at tlsgd
+R_PPC_GOT_TLSGD16_LO 80 half16 (sym+add)@got at tlsgd@l
+R_PPC_GOT_TLSGD16_HI 81 half16 (sym+add)@got at tlsgd@h
+R_PPC_GOT_TLSGD16_HA 82 half16 (sym+add)@got at tlsgd@ha
+R_PPC_GOT_TLSLD16 83 half16* (sym+add)@got at tlsld
+R_PPC_GOT_TLSLD16_LO 84 half16 (sym+add)@got at tlsld@l
+R_PPC_GOT_TLSLD16_HI 85 half16 (sym+add)@got at tlsld@h
+R_PPC_GOT_TLSLD16_HA 86 half16 (sym+add)@got at tlsld@ha
+R_PPC_GOT_TPREL16 87 half16* (sym+add)@got at tprel
+R_PPC_GOT_TPREL16_LO 88 half16 (sym+add)@got at tprel@l
+R_PPC_GOT_TPREL16_HI 89 half16 (sym+add)@got at tprel@h
+R_PPC_GOT_TPREL16_HA 90 half16 (sym+add)@got at tprel@ha
+
+(sym+add)@tls
+Merely causes the R_PPC_TLS marker reloc to be emitted.
+
+(sym+add)@dtpmod
+Computes the load module index of the load module that contains the
+definition of sym. The addend, if present, is ignored.
+
+(sym+add)@dtprel
+Computes a dtv-relative displacement, the difference between the value
+of sym+add and the base address of the thread-local storage block that
+contains the definition of sym, minus 0x8000. The minus 0x8000 is because
+dtv elements point to the start of the storage block plus 0x8000.
+
+(sym+add)@tprel
+Computes a tp-relative displacement, the difference between the value of
+sym+add and the value of the thread pointer (r2).
+
+(sym+add)@got at tlsgd
+Allocates two contiguous entries in the GOT to hold a tls_index structure,
+with values (sym+add)@dtpmod and (sym+add)@dtprel, and computes the offset
+of the first entry within the GOT.
+
+(sym+add)@got at tlsld
+Allocates two contiguous entries in the GOT to hold a tls_index structure,
+with values (sym+add)@dtpmod and zero, and computes the offset of the first
+entry within the GOT.
+
+(sym+add)@got at tprel
+Allocates an entry in the GOT with value (sym+add)@tprel, and computes the
+offset of the entry within the GOT.
+
+ at l, @h
+These modifiers affect the value computed, returning the low 16 bits or the
+high 16 bits of a 32 bit value.
+
+ at ha
+This modifier is like the corresponding @h modifier, except it adjusts for
+ at l being treated as a signed number.
+
+Relocations not using these modifiers (those flagged with `*' above) will
+trigger a relocation failure if the value computed does not fit in the
+field specified.
+
+Local variables:
+fill-column: 75
+End:
diff --git a/docs/tls-ppc64.txt b/docs/tls-ppc64.txt
new file mode 100644
index 0000000..79ec1de
--- /dev/null
+++ b/docs/tls-ppc64.txt
@@ -0,0 +1,547 @@
+PowerPC64 Specific Thread Local Storage ABI
+For insertion in http://people.redhat.com/drepper/tls.pdf
+
+
+3.4.x PowerPC64 Specific
+-------------------------
+
+The PowerPC64 TLS ABI is similar to the Alpha model. The thread-local
+storage data structures follow variant I. The TCB, tlsoffset calculations
+and definition of __tls_get_addr are identical to Alpha. r13 is the thread
+pointer, and points 0x7000 past the end of the thread control block.
+Dynamic thread vector pointers point 0x8000 past the start of each TLS
+block. (*) This allows the first 64K of each block to be addressed from a
+dtv pointer using fewer machine instructions. The tp offset allows for
+efficient addressing of the TCB and up to 4K-16 of other thread library
+information.
+
+(*) For implementation reasons the actual value stored in dtv may point to
+the start of a block, however values returned by accessor functions will be
+offset by 0x8000.
+
+
+4.1.x PowerPC64 General Dynamic TLS Model
+------------------------------------------
+
+The PowerPC64 general dynamic access model is similar to that for Alpha.
+The __tls_get_addr function is called with one parameter which is a pointer
+to an object of type tls_index. One complication is that two different
+assembly language syntaxes are used when referring to the GOT, one more
+compatible with other ELF systems, and one more compatible with PowerOpen
+systems. Furthermore, different parts of the tool-chain fill in the GOT
+(or TOC) in each mode. First we describe the ELF form and relocations.
+
+Code sequence Reloc Sym
+ addi 3,2,x at got@tlsgd R_PPC64_GOT_TLSGD16 x
+ bl .__tls_get_addr R_PPC64_REL24 .__tls_get_addr
+ nop
+
+GOT[n] R_PPC64_DTPMOD64 x
+GOT[n+1] R_PPC64_DTPREL64 x
+
+The relocation specifier @got at tlsgd causes the linker to create an object
+of type tls_index in the GOT. The address of this object is loaded into
+the first argument register with the addi instruction, then a standard
+function call is made.
+
+Now the PowerOpen compatible syntax, as used by PowerPC64 GCC.
+
+Code sequence Reloc Sym
+ addi 3,2,.LC0 at toc R_PPC64_TOC16 .LC0
+ bl .__tls_get_addr R_PPC64_REL24 .__tls_get_addr
+ nop
+..
+ .section .toc,"aw"
+.LC0:
+ .quad x at dtpmod R_PPC64_DTPMOD64 x
+ .quad x at dtprel R_PPC64_DTPREL64 x
+
+In this case, the TOC section contents are specified by the compiler; The
+linker doesn't create GOT entries. A minor variation on this code is used
+if -mminimal-toc is specified, but since the difference is common with
+other TOC code emitted by gcc it won't be described here.
+
+
+4.2.x PowerPC64 Local Dynamic TLS Model
+----------------------------------------
+
+This is similar to other architectures. As for Alpha, three different
+sequences may be used, depending on the size of the offset to the variable.
+First the ELF syntax.
+
+Code sequence Reloc Sym
+ addi 3,2,x1 at got@tlsld R_PPC64_GOT_TLSLD16 x1
+ bl .__tls_get_addr R_PPC64_REL24 .__tls_get_addr
+ nop
+..
+ addi 9,3,x1 at dtprel R_PPC64_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC64_DTPREL16_HA x2
+ addi 9,9,x2 at dtprel@l R_PPC64_DTPREL16_LO x2
+..
+ ld 9,x3 at got@dtprel(2) R_PPC64_GOT_DTPREL16_DS x3
+ add 9,9,3
+
+GOT[n] R_PPC64_DTPMOD64 x1
+GOT[n+1] 0
+
+GOT[m] R_PPC64_DTPREL64 x3
+
+ at got@tlsld in the first instruction causes the linker to generate a
+tls_index object in the GOT with a fixed 0 offset. Similarly, @got at dtprel
+causes the linker to generate a GOT entry for the dtv pointer offset. The
+code shown assumes that x1 is in the first 64k of the thread storage block,
+while x2 isn't but is within the first 2G, and x3 is outside 2G. If we
+wanted to load the values of x1, x2 and x3 instead of the address, then we
+could access unsigned int variables with
+
+..
+ lwz 0,x1 at dtprel(3) R_PPC64_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC64_DTPREL16_HA x2
+ lwz 0,x2 at dtprel@l(9) R_PPC64_DTPREL16_LO x2
+..
+ ld 9,x3 at got@dtprel(2) R_PPC64_GOT_DTPREL16_DS x3
+ lwzx 0,3,9
+
+Now the PowerOpen compatible syntax, as used by PowerPC64 GCC.
+
+Code sequence Reloc Sym
+ addi 3,2,.LC0 at toc R_PPC64_TOC16 .LC0
+ bl .__tls_get_addr R_PPC64_REL24 .__tls_get_addr
+ nop
+..
+ addi 9,3,x1 at dtprel R_PPC64_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC64_DTPREL16_HA x2
+ addi 9,9,x2 at dtprel@l R_PPC64_DTPREL16_LO x2
+..
+ ld 9,.LC1 at toc(2) R_PPC64_TOC16_DS .LC1
+ add 9,9,3
+..
+ .section .toc,"aw"
+.LC0:
+ .quad x1 at dtpmod R_PPC64_DTPMOD64 x1
+ .quad 0
+.LC1:
+ .quad x3 at dtprel R_PPC64_DTPREL64 x3
+
+No surprises here. As for the general dynamic code, the compiler handles
+generation of the tls_index object in the TOC.
+
+
+4.3.x PowerPC64 Initial Exec TLS Model
+---------------------------------------
+
+First the ELF version.
+
+Code sequence Reloc Sym
+ ld 9,x at got@tprel(2) R_PPC64_GOT_TPREL16_DS x
+ add 9,9,x at tls R_PPC64_TLS x
+
+GOT[n] R_PPC64_TPREL64 x
+
+ at got@tprel in the first instruction causes the linker to generate a GOT
+entry with a relocation that the dynamic linker will replace with the
+offset for x relative to the thread pointer. x at tls tells the assembler to
+use an r13 form of the instruction (ie. add 9,9,13 in this case), and tag
+the instruction with a reloc that indicates it belongs to a TLS sequence.
+This may be later used by the linker when optimizing TLS code.
+
+To read the contents of the variable instead of calculating its address,
+the "add 9,9,x at tls" instruction might be replaced with "lwzx 0,9,x at tls".
+
+The PowerOpen compatible version is similar, except that the compiler
+generates a TOC entry rather than the linker generating a GOT entry.
+
+Code sequence Reloc Sym
+ ld 9,.LC0 at toc(2) R_PPC64_TOC16_DS .LC0
+ add 9,9,.LC0 at tls R_PPC64_TLS .LC0
+..
+ .section .toc,"aw"
+.LC0:
+ .quad x at tprel R_PPC64_TPREL64 x
+
+
+4.4.x PowerPC64 Local Exec TLS Model
+-------------------------------------
+
+As for Alpha, three different sequences may be used, depending on the size
+of the offset to the variable. The first two handle offsets within 60K
+and 2G+28K respectively of the start of the TLS block (remember that r13
+points 28K past the end of the TCB, which is immediately prior to the first
+TLS block). The last sequence is identical to the Initial Execution TLS
+Model sequence so is not shown here.
+
+Code sequence Reloc Sym
+ addi 9,13,x1 at tprel R_PPC64_TPREL16 x1
+..
+ addis 9,13,x2 at tprel@ha R_PPC64_TPREL16_HA x2
+ addi 9,9,x2 at tprel@l R_PPC64_TPREL16_LO x2
+
+Since these two code sequences don't use the GOT, the PowerOpen compatible
+syntax is identical.
+
+5.x PowerPC64 Linker Optimizations
+-----------------------------------
+
+Linker transformations for PowerPC64 are complicated by there being two
+assembler syntaxes. When using the PowerPC64 ELF flavour syntax, GOT
+generation is under control of the linker, so it is possible to remove and
+replace unused GOT entries. For instance, the GD -> IE transformation
+results in two entries (a DTPMOD64 and DTPREL64) being replaced with a
+single TPREL64 entry. The transformation process is considerably more
+difficult for the linker when using the PowerOpen compatible syntax, as the
+linker needs to search TOC section relocs to map from the local sym (.LC0
+and .LC1 in the examples) to the variable. Currently, no compaction of the
+TOC is done by the linker when transforming PowerOpen compatible code, and
+it is fortunate that if transforming for a given symbol that we transform
+all references for the symbol. If that were not the case, we might need to
+add to the TOC rather than just modify an entry.
+
+5.x.1 General Dynamic To Initial Exec, ELF syntax
+--------------------------------------------------
+
+Code sequence Reloc Sym
+ addi 3,2,x at got@tlsgd R_PPC64_GOT_TLSGD16 x
+ bl .__tls_get_addr R_PPC64_REL24 .__tls_get_addr
+ nop
+
+GOT[n] R_PPC64_DTPMOD64 x
+GOT[n+1] R_PPC64_DTPREL64 x
+
+is replaced by
+
+ ld 3,x at got@tprel(2) R_PPC64_GOT_TPREL16_DS x
+ nop
+ add 3,3,13
+
+GOT[n] R_PPC64_TPREL64 x
+
+The linker relies on code being emitted exactly as shown.
+
+5.x.2 General Dynamic To Local Exec, ELF syntax
+------------------------------------------------
+
+This transformation is only performed by the linker when the symbol is
+within 2G+28K of the thread pointer. In other cases, the GD ->IE
+transformation is used as that handles any offset.
+
+Code sequence Reloc Sym
+ addi 3,2,x at got@tlsgd R_PPC64_GOT_TLSGD16 x
+ bl .__tls_get_addr R_PPC64_REL24 .__tls_get_addr
+ nop
+
+GOT[n] R_PPC64_DTPMOD64 x
+GOT[n+1] R_PPC64_DTPREL64 x
+
+is replaced by
+
+ addis 3,13,x at tprel@ha R_PPC64_TPREL16_HA x
+ nop
+ addi 3,3,x at tprel@l R_PPC64_TPREL16_LO x
+
+The linker relies on code being emitted exactly as shown.
+
+5.x.3 Local Dynamic to Local Exec, ELF syntax
+----------------------------------------------
+
+In this case, the function call is replaced with an equivalent code
+sequence. As shown, following dtprel sequences are left unchanged.
+
+Code sequence Reloc Sym
+ addi 3,2,x1 at got@tlsld R_PPC64_GOT_TLSLD16 x1
+ bl .__tls_get_addr R_PPC64_REL24 .__tls_get_addr
+ nop
+..
+ addi 9,3,x1 at dtprel R_PPC64_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC64_DTPREL16_HA x2
+ addi 9,9,x2 at dtprel@l R_PPC64_DTPREL16_LO x2
+..
+ ld 9,x3 at got@dtprel(2) R_PPC64_GOT_DTPREL16_DS x3
+ add 9,9,3
+
+GOT[n] R_PPC64_DTPMOD64 x1
+GOT[n+1]
+
+GOT[m] R_PPC64_DTPREL64 x3
+
+is replaced by
+
+ addis 3,13,L at tprel@ha R_PPC64_TPREL16_HA linker generated local sym
+ nop
+ addi 3,3,L at tprel@l R_PPC64_TPREL16_LO linker generated local sym
+..
+ addi 9,3,x1 at dtprel R_PPC64_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC64_DTPREL16_HA x2
+ addi 9,9,x2 at dtprel@l R_PPC64_DTPREL16_LO x2
+..
+ ld 9,x3 at got@dtprel(2) R_PPC64_GOT_DTPREL16_DS x3
+ add 9,9,3
+
+GOT[m] R_PPC64_DTPREL64 x3
+
+The "linker generated local sym" points to the start of the thread storage
+block plus 0x7000. In practice, a section symbol with a suitable offset
+will be used. The linker relies on code for the tls_get_addr call being
+emitted exactly as shown.
+
+5.x.4 Initial Exec To Local Exec, ELF syntax
+---------------------------------------------
+
+This transformation is only performed by the linker when the symbol is
+within 2G+28K of the thread pointer.
+
+Code sequence Reloc Sym
+ ld 9,x at got@tprel(2) R_PPC64_GOT_TPREL16_DS x
+ add 9,9,x at tls R_PPC64_TLS x
+
+GOT[n] R_PPC64_TPREL64 x
+
+is replaced by
+
+ addis 9,13,x at tprel@ha R_PPC64_TPREL16_HA x
+ addi 9,9,x at tprel@l R_PPC64_TPREL16_LO x
+
+Other sizes and types of thread-local variables may use any of the X-form
+indexed loads or stores that have corresponding D-form instructions. The
+"ld" and "add" instruction in this case may have intervening code inserted
+by the compiler.
+
+An example showing access to the contents of a variable:
+
+Code sequence Reloc Sym
+ ld 9,x at got@tprel(2) R_PPC64_GOT_TPREL16_DS x
+ lbzx 10,9,x at tls R_PPC64_TLS x
+ addi 10,10,1
+ stbx 10,9,x at tls R_PPC64_TLS x
+
+GOT[n] R_PPC64_TPREL64 x
+
+is replaced by
+
+ addis 9,13,x at tprel@ha R_PPC64_TPREL16_HA x
+ lbz 10,x at tprel@l(9) R_PPC64_TPREL16_LO x
+ addi 10,10,1
+ stb 10,x at tprel@l(9) R_PPC64_TPREL16_LO x
+
+5.x.5 General Dynamic To Initial Exec, PowerOpen syntax
+--------------------------------------------------------
+
+Code sequence Reloc Sym
+ addi 3,2,.LC0 at toc R_PPC64_TOC16 .LC0
+ bl .__tls_get_addr R_PPC64_REL24 .__tls_get_addr
+ nop
+..
+ .section .toc,"aw"
+.LC0:
+ .quad x at dtpmod R_PPC64_DTPMOD64 x
+ .quad x at dtprel R_PPC64_DTPREL64 x
+
+is replaced by
+
+ ld 9,.LC0 at toc(2) R_PPC64_TOC16_DS .LC0
+ nop
+ add 9,9,13
+..
+ .section .toc,"aw"
+.LC0:
+ .quad x at tprel R_PPC64_TPREL64 x
+ .quad 0
+
+5.x.6 General Dynamic To Local Exec, PowerOpen syntax
+------------------------------------------------------
+
+As for the ELF syntax, this transformation is only performed by the linker
+when the symbol is within 2G+28K of the thread pointer. In other cases,
+the GD ->IE transformation is used as that handles any offset.
+
+Code sequence Reloc Sym
+ addi 3,2,.LC0 at toc R_PPC64_TOC16 .LC0
+ bl .__tls_get_addr R_PPC64_REL24 .__tls_get_addr
+ nop
+..
+ .section .toc,"aw"
+.LC0:
+ .quad x at dtpmod R_PPC64_DTPMOD64 x
+ .quad x at dtprel R_PPC64_DTPREL64 x
+
+is replaced by
+
+ addis 3,13,x at tprel@ha R_PPC64_TPREL16_HA x
+ nop
+ addi 3,3,x at tprel@l R_PPC64_TPREL16_LO x
+..
+ .section .toc,"aw"
+.LC0:
+ .quad 1
+ .quad 0
+
+5.x.7 Local Dynamic to Local Exec, PowerOpen syntax
+----------------------------------------------------
+
+As above, the function call is replaced with an equivalent code
+sequence. Following dtprel sequences are left unchanged.
+
+Code sequence Reloc Sym
+ addi 3,2,.LC0 at toc R_PPC64_TOC16 .LC0
+ bl .__tls_get_addr R_PPC64_REL24 .__tls_get_addr
+ nop
+..
+ addi 9,3,x1 at dtprel R_PPC64_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC64_DTPREL16_HA x2
+ addi 9,9,x2 at dtprel@l R_PPC64_DTPREL16_LO x2
+..
+ ld 9,.LC1 at toc(2) R_PPC64_TOC16_DS .LC1
+ add 9,9,3
+..
+ .section .toc,"aw"
+.LC0:
+ .quad x1 at dtpmod R_PPC64_DTPMOD64 x1
+ .quad 0
+.LC1:
+ .quad x3 at dtprel R_PPC64_DTPREL64 x3
+
+is replaced by
+
+ addis 3,13,L at tprel@ha R_PPC64_TPREL16_HA linker generated local sym
+ nop
+ addi 3,3,L at tprel@l R_PPC64_TPREL16_LO linker generated local sym
+..
+ addi 9,3,x1 at dtprel R_PPC64_DTPREL16 x1
+..
+ addis 9,3,x2 at dtprel@ha R_PPC64_DTPREL16_HA x2
+ addi 9,9,x2 at dtprel@l R_PPC64_DTPREL16_LO x2
+..
+ ld 9,.LC1 at toc(2) R_PPC64_TOC16_DS .LC1
+ add 9,9,3
+..
+ .section .toc,"aw"
+.LC0:
+ .quad 1
+ .quad 0
+.LC1:
+ .quad x3 at dtprel R_PPC64_DTPREL64 x3
+
+5.x.8 Initial Exec To Local Exec, PowerOpen syntax
+---------------------------------------------------
+
+As for the ELF syntax, this transformation is only performed by the linker
+when the symbol is within 2G+28K of the thread pointer.
+
+Code sequence Reloc Sym
+ ld 9,.LC0 at toc(2) R_PPC64_TOC16_DS .LC0
+ add 9,9,.LC0 at tls R_PPC64_TLS .LC0
+..
+ .section .toc,"aw"
+.LC0:
+ .quad x at tprel R_PPC64_TPREL64 x
+
+is replaced by
+
+ addis 9,13,x at tprel@ha R_PPC64_TPREL16_HA x
+ addi 9,9,x at tprel@l R_PPC64_TPREL16_LO x
+..
+ .section .toc,"aw"
+.LC0:
+ .quad 0
+
+
+6.x New PowerPC64 ELF Definitions
+----------------------------------
+
+Reloc Name Value Field Expression
+R_PPC64_TLS 67 none (sym+add)@tls
+R_PPC64_DTPMOD64 68 doubleword64 (sym+add)@dtpmod
+R_PPC64_TPREL16 69 half16* (sym+add)@tprel
+R_PPC64_TPREL16_LO 60 half16 (sym+add)@tprel at l
+R_PPC64_TPREL16_HI 71 half16 (sym+add)@tprel at h
+R_PPC64_TPREL16_HA 72 half16 (sym+add)@tprel at ha
+R_PPC64_TPREL64 73 doubleword64 (sym+add)@tprel
+R_PPC64_DTPREL16 74 half16* (sym+add)@dtprel
+R_PPC64_DTPREL16_LO 75 half16 (sym+add)@dtprel at l
+R_PPC64_DTPREL16_HI 76 half16 (sym+add)@dtprel at h
+R_PPC64_DTPREL16_HA 77 half16 (sym+add)@dtprel at ha
+R_PPC64_DTPREL64 78 doubleword64 (sym+add)@dtprel
+R_PPC64_GOT_TLSGD16 79 half16* (sym+add)@got at tlsgd
+R_PPC64_GOT_TLSGD16_LO 80 half16 (sym+add)@got at tlsgd@l
+R_PPC64_GOT_TLSGD16_HI 81 half16 (sym+add)@got at tlsgd@h
+R_PPC64_GOT_TLSGD16_HA 82 half16 (sym+add)@got at tlsgd@ha
+R_PPC64_GOT_TLSLD16 83 half16* (sym+add)@got at tlsld
+R_PPC64_GOT_TLSLD16_LO 84 half16 (sym+add)@got at tlsld@l
+R_PPC64_GOT_TLSLD16_HI 85 half16 (sym+add)@got at tlsld@h
+R_PPC64_GOT_TLSLD16_HA 86 half16 (sym+add)@got at tlsld@ha
+R_PPC64_GOT_TPREL16_DS 87 half16ds* (sym+add)@got at tprel
+R_PPC64_GOT_TPREL16_LO_DS 88 half16ds (sym+add)@got at tprel@l
+R_PPC64_GOT_TPREL16_HI 89 half16 (sym+add)@got at tprel@h
+R_PPC64_GOT_TPREL16_HA 90 half16 (sym+add)@got at tprel@ha
+R_PPC64_GOT_DTPREL16_DS 91 half16ds* (sym+add)@got at dtprel
+R_PPC64_GOT_DTPREL16_LO_DS 92 half16ds (sym+add)@got at dtprel@l
+R_PPC64_GOT_DTPREL16_HI 93 half16 (sym+add)@got at dtprel@h
+R_PPC64_GOT_DTPREL16_HA 94 half16 (sym+add)@got at dtprel@ha
+R_PPC64_TPREL16_DS 95 half16ds* (sym+add)@tprel
+R_PPC64_TPREL16_LO_DS 96 half16ds (sym+add)@tprel at l
+R_PPC64_TPREL16_HIGHER 97 half16 (sym+add)@tprel at higher
+R_PPC64_TPREL16_HIGHERA 98 half16 (sym+add)@tprel at highera
+R_PPC64_TPREL16_HIGHEST 99 half16 (sym+add)@tprel at highest
+R_PPC64_TPREL16_HIGHESTA 100 half16 (sym+add)@tprel at highesta
+R_PPC64_DTPREL16_DS 101 half16ds* (sym+add)@dtprel
+R_PPC64_DTPREL16_LO_DS 102 half16ds (sym+add)@dtprel at l
+R_PPC64_DTPREL16_HIGHER 103 half16 (sym+add)@dtprel at higher
+R_PPC64_DTPREL16_HIGHERA 104 half16 (sym+add)@dtprel at highera
+R_PPC64_DTPREL16_HIGHEST 105 half16 (sym+add)@dtprel at highest
+R_PPC64_DTPREL16_HIGHESTA 106 half16 (sym+add)@dtprel at highesta
+
+(sym+add)@tls
+Merely causes the R_PPC64_TLS marker reloc to be emitted.
+
+(sym+add)@dtpmod
+Computes the load module index of the load module that contains the
+definition of sym. The addend, if present, is ignored.
+
+(sym+add)@dtprel
+Computes a dtv-relative displacement, the difference between the value
+of sym+add and the base address of the thread-local storage block that
+contains the definition of sym, minus 0x8000. The minus 0x8000 is because
+dtv elements point to the start of the storage block plus 0x8000.
+
+(sym+add)@tprel
+Computes a tp-relative displacement, the difference between the value of
+sym+add and the value of the thread pointer (r13).
+
+(sym+add)@got at tlsgd
+Allocates two contiguous entries in the GOT to hold a tls_index structure,
+with values (sym+add)@dtpmod and (sym+add)@dtprel, and computes the offset
+to the first entry relative to the TOC base (r2).
+
+(sym+add)@got at tlsld
+Allocates two contiguous entries in the GOT to hold a tls_index structure,
+with values (sym+add)@dtpmod and zero, and computes the offset to the first
+entry relative to the TOC base (r2).
+
+(sym+add)@got at dtprel
+Allocates an entry in the GOT with value (sym+add)@dtprel, and computes the
+offset to the entry relative to the TOC base (r2).
+
+(sym+add)@got at tprel
+Allocates an entry in the GOT with value (sym+add)@tprel, and computes the
+offset to the entry relative to the TOC base (r2).
+
+ at l, @h, @higher, @highest
+These modifiers affect the value computed, returning the low 16 bits, the
+next 16 bits, and so on up to the top 16 bits of a 64 bit value.
+
+ at ha, @highera, @highesta
+These modifiers are like the corresponding @h, @higher and @highest
+modifiers, except they adjust for @l being treated as a signed number.
+
+Relocations not using these modifiers (those flagged with `*' above) will
+trigger a relocation failure if the value computed does not fit in the
+field specified.
+
+Local variables:
+fill-column: 75
+End:
diff --git a/docs/tls.pdf b/docs/tls.pdf
new file mode 100644
index 0000000..74402ef
Binary files /dev/null and b/docs/tls.pdf differ
diff --git a/header.html b/header.html
index 02cb23f..ff2b070 100644
--- a/header.html
+++ b/header.html
@@ -53,6 +53,7 @@
<b>Documentation</b>
<ul>
<li><a href="/FAQ.html">FAQ</a></li>
+ <li><a href="/specs.html">Specifications</a></li>
</ul>
<b>Obtain</b>
<ul>
diff --git a/specs.html b/specs.html
new file mode 100644
index 0000000..fe27d82
--- /dev/null
+++ b/specs.html
@@ -0,0 +1,79 @@
+<!--#include file="header.html" -->
+
+
+<h3>Specifications</h3>
+
+<p>
+Implementing a compliant C library requires knowledge across many areas.
+Here you can find relevant specifications that'll help you in your quest.
+If you know of other things that could be useful, please
+<a href="/lists.html">let us know</a>!
+
+<p>
+These are standards to be aware of; generally uClibc aims to be compliant
+with the latest POSIX standard.
+<ul>
+<li><a href="http://pubs.opengroup.org/onlinepubs/9699919799/">POSIX 1003.1 2008 (Issue 7)</a>
+<li><a href="http://pubs.opengroup.org/onlinepubs/009695399/">POSIX 1003.1 2004 (Issue 6)</a>
+<li><a href="/docs/SysV-ABI.pdf">SystemV ABI</a>
+<li><a href="/docs/SysV-Interface-vol1a.pdf">SystemV Interface (volume 1a)</a>
+<li><a href="/docs/SysV-Interface-vol1b.pdf">SystemV Interface (volume 1b)</a>
+<li><a href="/docs/SysV-Interface-vol2.pdf">SystemV Interface (volume 2)</a>
+</ul>
+
+<p>
+These are documents related to the common
+<a href="http://en.wikipedia.org/wiki/Executable_and_Linkable_Format">ELF</a>
+format.
+<ul>
+<li><a href="/docs/elf.pdf">ELF (version 1.2)</a>
+<li><a href="/docs/elf-64-gen.pdf">ELF 64-bit</a>
+<li><a href="http://www.sco.com/developers/gabi/">ELF Generic ABI</a>
+<li><a href="/docs/tls.pdf">Thread Local Storage (TLS)</a> (note: also contains alpha ia64 s390 s390x sh x86 x86-64)
+
+</ul>
+
+<p>
+These are architecture-specific ELF documents.
+<ul>
+<li><a href="/docs/psABI-arm.pdf">psABI ARM</a>
+<li><a href="http://docs.blackfin.uclinux.org/doku.php?id=toolchain:application_binary_interface">psABI Blackfin</a>
+<li><a href="/docs/psABI-i386.pdf">psABI Intel386 (x86)</a>
+<li><a href="/docs/psABI-ia64.pdf">psABI Itanium (ia64)</a>
+<li><a href="/docs/psABI-m8-16.pdf">psABI m68k (8bit & 16bit)</a>
+<li><a href="/docs/psABI-mips.pdf">psABI mips</a>
+<li><a href="/docs/psABI-parisc.pdf">psABI PA-RISC (HP/PA)</a>
+<li><a href="/docs/psABI-ppc.pdf">psABI PowerPC</a>
+ <a href="/docs/tls-ppc.txt">TLS</a>
+<li><a href="/docs/psABI-ppc64.pdf">psABI PowerPC64</a>
+ <a href="/docs/tls-ppc64.txt">TLS</a>
+<li><a href="/docs/psABI-s390.pdf">psABI s/390</a>
+<li><a href="/docs/psABI-s390x.pdf">psABI s/390x</a>
+<li><a href="/docs/psABI-sh.txt">psABI SuperH</a>
+<li><a href="/docs/psABI-sparc.pdf">psABI SPARC</a>
+<li><a href="/docs/psABI-x86_64.pdf">psABI AMD64 (x86_64)</a>
+</ul>
+
+<p>
+These are general architecture related reference manuals.
+<ul>
+<li><a href="http://en.wikibooks.org/wiki/Subject:Assembly_languages">Wikibooks: Assembly languages</a>
+<li><a href="http://h18002.www1.hp.com/cpq-alphaserver/technology/literature/alphaahb.pdf">Alpha</a>
+ <a href="http://h18002.www1.hp.com/alphaserver/technology/chip-docs.html">(General)</a>
+<li><a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architecture/index.html">ARM</a>
+<li><a href="http://www.analog.com/static/imported-files/processor_manuals/Blackfin_pgr_rev2.0.pdf">Blackfin</a>
+ <a href="http://www.analog.com/en/processors-dsp/blackfin/processors/manuals/resources/index.html">(General)</a>
+<li><a href="http://h21007.www2.hp.com/dspp/tech/tech_TechByTypePage_IDX/1,4690,40106-0,00.html">PA-RISC (HP/PA)</a>
+<li><a href="http://www.freescale.com/files/archives/doc/ref_manual/M68000PRM.pdf">m68k</a>
+<li><a href="http://www.mips.com/products/product-materials/processor/mips-architecture/">mips</a>
+<li><a href="http://www.power.org/resources/downloads/PowerISA_V2.06B_V2_PUBLIC.pdf">PowerPC</a>
+ <a href="http://www.ibm.com/developerworks/systems/library/es-archguide-v2.html">(more)</a>
+<li><a href="http://lars.nocrew.org/computers/processors/ESA390/dz9zr002.pdf">s/390</a>
+<li><a href="http://www.sparc.org/specificationsDocuments.html">SPARC</a>
+<li>x86
+ <a href="http://developer.amd.com/documentation/guides/pages/default.aspx">AMD</a>
+ <a href="http://www.intel.com/products/processor/manuals/">Intel</a>
+<li><a href="http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm">xtensa</a>
+</ul>
+
+<!--#include file="footer.html" -->
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